A system on a chip (SOC) is an integrated circuit that integrates the various components of a computer or other electronic system onto a single substrate. A typical SOC includes one or more microprocessor cores, non-volatile memory, volatile memory, clock signal generators, peripheral interfaces, voltage regulators, external digital interfaces, and external analog interfaces.
Due to temperature, age, operating conditions, or external attacks, a SOC may operate improperly, and such improper operation may be referred to as a “glitch”. By monitoring or analyzing the main clock of the SOC, such glitches can be detected.
Sample types of glitches that can be detected are shown in the timing diagram of FIG. 1. Here, first note the glitch labeled “1”—this is the type of glitch resulting from a spurious rising of the clock signal, which can lead to a setup violation or other incorrect operation of a SOC. Similarly, another type of glitch can result from the clock signal running at an unintended frequency, such as being inadvertently overclocked.
Still another type of glitch that can be detected is the delay of data due to variations in the threshold of transistors due to age or other factors. One example of this is shown as the glitch labeled “2”, where the data should be latched at the rising edges of the clock signal, but instead is latched a delay period after the rising edges of the clock signal.
A further type of glitch that can be detected is the shifting of edges of the clock signal due to electromagnetic interference, shown here as the glitch labeled “3”. Note that this glitch is particularly concerning, as the shifting of clock edges can result in data signal shifting and setup violations, among other issues.
A first prior art glitch detector 50 is shown in FIG. 2A. This glitch detector 50 is incorporated within a SOC 49. By being incorporated within the SOC 49, the glitch detector 50 can be assumed to be subject to the same glitches as the SOC 49, and therefore proper or improper operation of the SOC 49 can be inferred from output of the glitch detector 50.
The glitch detector 50 is comprised of an input flip flop 51, a delay chain 52, a first output flip flop 53, a second output flip flop 54, an XOR gate 55, and a finite state machine (FSM) 56. In greater detail, the input flip flop 51 receives the SOC clock signal CLK at its clock input, receives the output of its QN output at its D input, and has its Q output coupled to an input of the delay chain 52. The delay chain 52 has delay elements 52a . . . 52d selectable in number by the finite state machine 56. The first output flip flop 53 receives the SOC clock signal CLK at its clock input, receives output from the delay chain 52 (the CLK_div2 delay signal) at its D input, and has its Q output coupled to the exclusive-OR (XOR) gate 55. The second output flip flop 54 receives the SOC clock signal CLK at its clock input, receives output from the Q output of the input flip flop 51 (the CLK_div2 signal) at its D input, and has its Q output coupled to the XOR gate 55. The XOR gate, receiving the Q outputs of the first and second output flip flops 53 and 54 at its inputs, outputs a glitch detect flag Glitch_detect.
Each delay inserted by a delay block 52a-52d of the delay chain 52 is set to be equal to slightly less than the period of the SOC clock signal CLK. Therefore, if the Q outputs of the first output flip flop 53 and the second output flip flop 54 are equal at the rising edge of the SOC clock signal CLK, it can be inferred that there is not a glitch in the current operation of the SOC 49, and the Glitch_detect flag can accordingly indicate a lack of the glitch. However, if the Q outputs of the first output flip flop 53 and the second output flip flop 54 are not equal at the rising edge of the SOC clock signal CLK, it can be assumed that there has been a disturbance resulting in a glitch in the current operation of the SOC 49, and the Glitch_detect flag can accordingly indicate the presence of the glitch. Progressively increased delays of the SOC clock signal CLK can be seen in FIG. 2B.
Operation of the glitch detector 50 itself is shown in the timing diagram of FIG. 2C. Here, no glitch is present, as it can be noticed that the Q outputs of the first output flip flop 53 and second output flip flop 54 (respectively labeled Q.53 and Q.54) are equal at rising edges of the SOC clock signal CLK—stated another way, it can be seen that the CLK_div2 and CLK_div2 delay signals are equal at the rising edge of the SOC clock signal CLK, so there is no glitch detected.
Operation of the glitch detector 50 in the presence of a glitch is shown in the timing diagram of FIG. 2D. At time t1, it can be seen that CLK_div2 spuriously rises. The result of this is that the output of flip flop 54 (labeled as Q.54) does not fall at time t2 like it otherwise would. Therefore, between time t2 and t3, the output of flip flop 54 is high while the output of flip flop is low, with the result being that the XOR gate 55 outputs Glitch_detect as a logic high between times t2 and t3 to indicate occurrence of a glitch.
A second prior art glitch detector 50′ is shown in FIG. 3A. This glitch detector 50 is incorporated within a SOC 49. By being incorporated within the SOC 49, the glitch detector 50′ can be assumed to be subject to the same glitches as the SOC 49, and therefore operation of the circuitry of the glitch detector 50′ can indicate the presence of glitches with the operation of the SOC 49.
The glitch detector 50′ is comprised of a delay chain 52, an output flip flop 53, and a finite state machine (FSM) 56. The delay chain 52 has delay elements 52a . . . 52d selectable in number by the finite state machine 56, with the first delay element 52a receiving the data signal as input. The output flip flop 53 receives the delayed version of the data signal (delayed by the delay elements 52a . . . 52d) at its clock input, the (not delayed) data signal at its D input, and generates the Glitch_detect flag at its QN output (complement of the Q output). Note that there is a bubble at the CLK input, indicating that the delayed version of the data signal is inverted before being read by the output flip flop 53, having the effect of making the output flip flop 53 falling edge triggered with respect to the SOC clock signal CLK as opposed to rising edge triggered.
As can be appreciated, once glitch detection is begun, at each falling edge of the delayed version of the clock signal received at the clock input of the output flip flop 53, the data signal is latched as the Glitch_detect signal at the QN output of the output flip flop 53. Due to the delay, in the absence of a glitch, at each falling edge of the delayed version of the clock signal, the data signal should be at a logic high, and thus the Glitch_detect flag at the QN output of the output flip flop 53 should remain low, indicating a lack of a glitch. However, if there has been a glitch in the data signal that results in a rising edge of the data signal at an incorrect time, the delayed version of the clock signal also experiences that rising edge at an incorrect time, leading to the data signal being latched while it is at a logic low. This results in the Glitch_detect flag rising to indicate presence of a glitch.
This operation can be seen in FIG. 3B. At the first falling edge of the SOC clock signal CLK at time t1, the data signal is at a logic high, so Glitch_detect is latched at a logic low. At the second falling edge of the SOC clock signal CLK at time t2, which occurs due to the glitch # G1 showing up in the delayed version of the data signal as # G1_d, the data signal is at a logic low, so Glitch_detect is latched at a logic high to indicate presence of a glitch. At the third falling edge of the SOC clock signal CLK at time t3, the data signal is still at a logic high, therefore Glitch_detect is latched at a logic low. At the fourth falling edge of the SOC clock signal CLK at time t4, which occurs due to the glitch # G2 showing up in the delayed version of the data signal as # G2_d, the data signal is at a logic low, so Glitch_detect is latched at a logic high. Finally, at the fifth falling edge of the SOC clock signal CLK at time t5, the data signal is still at a logic high, so Glitch_detect is latched at a logic low. Therefore, it can be seen that the Glitch_detect signal has been latched high at times T2 and T4, which are times at which the glitches # G1_d and # G2_d riding on the delayed version of the data signal occur, but that the Glitch_detect signal has been latched low at times t1, t3, and t3, which are times at which no glitches are riding on the delayed version of the data signal.
While the glitch detectors 50 and 50′ shown in FIGS. 2 and 3A are effective in some scenarios, they suffer drawbacks that render their designs less than ideal. For example, if the delay of the delay chain 52 begins at a low value while operating temperature of the SOC 49 is high, is the temperature of the SOC 49 reduces, then the delay of the delay chain may become less than ideal, making it possible that the glitch detector 50 or 50′ fails to detect some (or any) glitches.
Therefore, further development into the area of glitch detectors is needed.